There are three main drivers for IC to package or board interconnects: high speed, unlimited I/O connections, and reparability. Compliant structures are essential to provide the interconnect reliability in fine-pitch wafer-level packaging. Yet, conventional approaches for interconnects, such as reflowed and electroplated solder interconnects, are limited in terms of either pitch or electrical properties. For example, solder bumps can only give thick (>50 micron interconnects) along with serious reliability problems.
Yet, with finer pitch, there is a large increase in the stresses at interconnect joints. Conventional compliant interconnect approaches to overcome this issue have complicated processing steps and the electrical properties are generally compromised to achieve the mechanical performance. These prior art attempts come with high cost and lengthy processing steps. For example, pure metallic interconnects or interconnects, even from newer materials such as carbon nanotubes, can result in higher interfacial shear and peeling stresses that also affect the mechanical reliability.
Known high-aspect-ratio structures concentrate on electroplating through micro-machined SU8 or other photoresist molds. Though SU8 can result in high-aspect-ratio structures, it does not have good mechanical properties to fabricate reliable MEMS structures.
Decreasing I/O pitch is one of the key technological barriers identified by the 2003 International Technology Roadmap for Semiconductors (ITRS) [1]. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Recently, MEMS-based compliant metallic structures are being widely explored for reliable and high I/O density chip-package interconnections [2-3]. The lateral compliance of such interconnects can easily accommodate the displacement caused by the CTE mismatch. These interconnects can deform elastically in response to thermal or mechanical loads, thereby potentially increasing the testability and reliability of assembled wafer level packages. The design of compliant interconnects is of critical importance in optimizing their electrical and mechanical characteristics. These characteristics are intrinsically linked and both depend on the geometry of the structures and the properties of the materials used.
As previously noted, conventional compliant interconnect approaches have very complicated processing steps [2] and the electrical properties are generally compromised to achieve the mechanical performance [3]. Achieving compliance with simple metallic structures is difficult because of their inherently high stiffness. Advanced polymers with ultra-low stiffness (on the order of 0.5 GPa) and Simatched CTE (3 ppm/°C.) are now being synthesized for on-chip interconnect and packaging applications. These polymers have 100-200 times lower stiffness than most metals, making it far easier to achieve compliance even with straight and short structures. Conductivity can be achieved with a metal coating on the polymer surface. Due to the skin effect, as long as the metal coating is large in thickness compared with the skin depth at the operating frequencies of interest, there is little to no degradation in electrical performance in polymer core structures compared to metallic structures.
Therefore, it can be seen that a need yet exists for an interconnect that can provide improved electrical performance while lowering the stresses at the interfaces by orders of magnitude. It is to such a structure, being a high-aspect-ratio metal-coated polymer structure, that the present invention is primarily directed. These polymer-based structures can also simplify the processing steps and result in tremendous cost reductions.